As is well known, a non-volatile memory is able to continuously retain data after the supplied power is interrupted. Generally, after the non-volatile memory leaves the factory, the non-volatile memory may be programmed by the user. After the non-volatile memory is programmed, data are recorded into the non-volatile memory. Moreover, depending on the programmable times, non-volatile memories may be classified into two types, i.e. a multi-time programming memory (also referred as a MTP memory) and a one time programming memory (also referred as an OTP memory). Generally, the MTP memory can be programmed multiple times by the user. On the other hand, the OTP memory can be programmed once. After the OTP memory is programmed, the data stored in the OTP memory is hard to modify.
Moreover, a mask read-only memory (also referred as a Mask ROM) is another widely-used non-volatile memory. After the mask read-only memory leaves the factory, all stored data are recorded in the mask read-only memory. The data stored in the mask read-only memory can only be read by the user, but cannot be programmed by the user. That is, the stored data should be provided to the manufacturer of the mask read-only memory at first. After the mask read-only memory is fabricated by the manufacturer and sent to the user, all stored data have been recorded into the mask read-only memory, and the mask read-only memory fails to be programmed.
Since the mask read-only memory has many advantages such as low cost, high reliability and high capability, the mask read-only memory has been widely applied to various electronic devices.
FIG. 1 is a schematic perspective view illustrating a conventional non-volatile semiconductor memory cell with dual functions. The conventional non-volatile semiconductor memory cell is disclosed in U.S. Pat. No. 8,344,445.
The memory cell 300 has a substrate with a P-well region 310. An active region 315 is formed in a surface of the P-well region 310. A gate oxide layer 321 is formed on the substrate, and a first polysilicon gate 313-1 is formed on the gate oxide layer 321. Another gate oxide layer 320 is formed on the substrate, and a second polysilicon gate 313-2, a third polysilicon gate 313-3 and a charge storage layer 314 are formed on the gate oxide layer 320.
The active region 315 is divided into a first N+ diffusion region 311-1, a second N+ diffusion region 311-2 and a third N+ diffusion region 311-3. The first N+ diffusion region 311-1 is located at a left side of the first polysilicon gate 313-1. The third N+ diffusion region 311-3 is arranged between the first polysilicon gate 313-1 and the second polysilicon gate 313-2. The second N+ diffusion region 311-2 is located at the right side of the second polysilicon gate 313-2 and the third polysilicon gate 313-3. Moreover, two contacts 316-1 and 316-2 are formed on the first N+ diffusion region 311-1 and the second N+ diffusion region 311-2, respectively.
The memory cell 300 as shown in FIG. 1 may be used as an OTP memory cell or a MTP memory cell. After an integrated circuit (IC) with such memory cells is acquired by the user, the integrated circuit (IC) may be used as an OTP memory or a MTP memory to be programmed. However, the non-volatile semiconductor memory cell as shown in FIG. 1 is not a mask read-only memory cell.